1. Field of the Invention
The exemplary embodiment of the present invention relate to a bit line sensing operation in a volatile semiconductor memory device.
2. Description of the Related Art
In general, as recent technology shifts toward high speed operations in semiconductor memory devices such as a dynamic random access memory (DRAM) etc. which are performed at a relatively low power, the voltage used to access data, (i.e., voltage needed for a read or write operation), is gradually lowering. Thus, as a data sensing margin becomes more critical, a bit line data sensing operation may become more susceptible to peripheral influences, such as noise, for example.
FIG. 1 is a circuit drawing illustrating a drive of a prior art bit line sense amplifier in a semiconductor memory device. Referring to FIG. 1, a plurality of bit line sense amplifiers (1,2, . . . ,n), each of which is composed of a pull-up P-type sense amplifier 4 and a pull-down N-type sense amplifier 5 that are connected to a bit line pair B/L and B/LB, share a precharge part 10. A first drive mode LA and a second drive node LAB of bit line sense amplifier 1 are individually connected to first and second precharge nodes of the precharge part 10. Thus, during a precharged state (i.e., a data non-access mode), the first and second drive nodes LA, LAB are equally precharged by a voltage source VBL applied to node no1. Also in this circuitry, a state of the bit line pair B/L, B/LB is generally precharged to a half voltage source by a bit line precharge circuit (not shown).
The circuit of FIG. 1 including the bit line sense amplifiers (1,2, . . . ,n) has been simplified for convenience of explanation. The circuit further includes an input/output gate part disposed between the P-type sense amplifier 4 and the N-type sense amplifier 5, and a memory cell array. The memory cell array typically may have a matrix shape, and may include unit memory cells formed at each of points crossed between word lines and the bit line pairs B/L, B/LB. Each unit memory cell may be composed of an access transistor and a storage capacitor, for example.
Although omitted for convenience of explanation, the circuit of FIG. 1 further includes an isolation element (not shown) disposed between the P-type sense amplifier 4 and its adjacent memory cell, and between the N-type sense amplifier 5 and its adjacent memory cell. The isolation element would be driven by each block selection signal to electrically isolate the bit line pair B/L, B/LB from an input/output gate line pair (not shown in FIG. 1 for clarity, but generally referred to as “I/O, I/OB”).
When an operating mode is changed from a precharge state (i.e., data non-access mode) to a data access mode, a P-type sense amplifier drive signal LAPG2 is applied as a logic level low, and an N-type sense amplifier drive signal LANG is applied as a logic level high. Then, an array voltage source Vcca applied from a power supply line part (not shown) is applied to first drive node LA of P-type sense amplifier 4 through a source/drain channel of a P-type MOS transistor PM1.
In FIG. 1, one of two voltage sources VDD and Vcca is selectively applied to the first drive node LA in a data access mode to enhance performance. When a system including a semiconductor memory device is powered on, a first P-type sense amplifier drive signal LAPG1 is initially applied as a logic level low, and a second P-type sense amplifier drive signal LAPG2 is applied as a logic level high. Then, upon a stable operation of the semiconductor memory device (i.e., when the memory device has powered up an stabilized)), LAPG1 becomes high and LAPG2 becomes low. The voltage source VDD is a external voltage source applied to the circuit of FIG. 1, and cell array voltage source Vcca is an internal voltage source stably generated from an array voltage source generator such as may be arranged on a semiconductor chip.
The N-type sense amplifier drive signal LANG becomes a logic level high, thus an N-type driver 40 (comprised of N-type MOS transistors (ND1,ND2, . . . ,NDn)) is turned on and voltage at second drive node LAB of the N-type sense amplifier 5 becomes a level of a ground voltage Vssa.
A pull-up operation of the P-type sense amplifier 4 is now explained. When the data access mode in the circuit of FIG. 1 is configured for a read operation, a row address strobe (RASB) is enabled and a word line selected by an address decoder (not shown) is activated. Therefore the charge of selected memory cells is transferred to corresponding bit line pairs, so as to induce a charge sharing operation among the bit line pairs. If a potential difference in a bit line pair occurs (i.e., between bit line B/L and complementary bit line B/LB), one of MOS transistors P1 and P2 of P-type sense amplifier 4 is turned on, so that potential of one of the bit lines (B/L or B/LB) rises to Vcca.
A pull-down operation of the N-type sense amplifier 5 is now described. During a read operation as described above, one of MOS transistors N1 and N2 of the N-type sense amplifier 5 whose gate is connected to the bit line that rises to Vcca, is strongly turned on to immediately rise to Vcca, as compared to another N-type MOS transistor in N-type sense amplifier 5 that is not connected to the bit line. Thus, in bit line pair B/L, B/LB, the potential of the other bit line (the other of B/L and B/LB that does not smartly rise to Vcca,) drops to Vssa.
Accordingly, sensing of the bit line data may thus be conducted in accordance with the pull-up and pull-down operations of the P-type sense amplifier 4 and N-type sense amplifier 5. The cell array voltage source Vcca applied to the first drive node LA, and the ground voltage source Vssa applied to the second drive node LAB of the bit line sense amplifier may be used as power sources for respective read or write operations in the memory cell array.
As described above, the bit line sense amplifiers (1 to n) share a precharge part 10, a P-type driver 20 and a P-type MOS transistor PM1. P-type driver 20 supplies a first voltage source (VDD) in response to the first P-type sense amplifier drive signal LAPG1. VDD is distributed to each sense amplifier 1 to n. The P-type MOS transistor PM1 supplies a second voltage source (Vcca) to sense amplifies 1 ton in response to the second P-type sense amplifier drive signal LAPG2.
The circuit of FIG. 1 may have a shortcoming, in that speed of a bit line data sensing operation may be degraded due to the influence of adjacent bit lines. One cause for the degradation of the sensing speed may be due to noise that may be prevalent in the sharing structure of the P-type driver 20 that includes P-type MOS transistor PM1, as shown in FIG. 1. However, recent technology has evolved to speed up sensing operations, in an effort to overcome the problems due to sharing the P-type MOS transistor PM1 in the circuit of FIG. 1.
FIG. 2 is a circuit drawing illustrating another drive of a prior art bit line sense amplifier in a semiconductor memory device. For consistency, like components in FIG. 2 maintain the same reference symbols as in FIG. 1, for except for additional or different components that are otherwise identified below.
Referring to FIG. 2, the precharge part 10 has been omitted and a second P-type driver 30 for independently supplying cell array voltage source Vcca to each bit line sense amplifier has been added. In other words, P-type MOS transistors (PD12, PD22, PDn2) of the second P-type driver 30 are disposed at each bit line pair (B/L, B/LB), thus there is no noise influence between the sense amplifiers 1 to n.
The circuit of FIG. 2 thus implements what may be referred to as an independent power drive method. The independent power drive method shown in FIG. 2 has a quicker bit line data sensing speed, as compared to circuit of FIG. 1, but voltage levels of the first and second drive nodes (LA, LAB) assume a floating state in the data non-access mode. This floating state, where voltages at LA and LAB may change, occurs because the circuit of FIG. 2 does not employ the precharge part 10 for precharging the first and second drive nodes (LA, LAB).
FIGS. 3a and 3b illustrate problems related to the drive of the prior art bit line sense amplifier shown in FIG. 2. Referring FIG. 3a, when noise is momentarily applied to the N-type driver 40 through a gate of an N-type MOS transistor ND1 (in this case, the second drive node LAB assumes a floating state in the data non-access mode), the N-type MOS transistor ND1 may be turned on. In this situation, if noise is applied to the N-type MOS transistor ND1 while receiving the N-type sense amplifier drive signal LANG through the gate of transistor ND1, potential of the second drive node LAB is reduced by a turn-on operation of transistor ND1. This may cause errors in a bit line data sensing operation. In other words, there may be a problem in that a pre-sensing operation is performed before a charge sharing operation, so as to cause a sensing error, for example.
FIG. 3b shows an example of a short occurring between the second drive node LAB and a line of the ground voltage Vssa, due to a manufacturing defect in the circuit of FIG. 2, for example. In this case, a sensing error may arise as described in the case of FIG. 3a. In FIG. 3b, if current noise is modeled through a current source (In0) between the second drive node LAB and the line of ground voltage Vssa, the debilitating influence of noise upon the sensing operation may be monitored. Accordingly, the independent power drive method implemented by the circuit of FIG. 2, may exhibit problems in which voltage levels of the first and second drive nodes assume a floating state in a data non-access mode. Thus, bit line data sensing cannot be stabilized.